RTL Design Engineer

RTL Design Engineer needed in a hybrid role (Moscow, Saint Petersburg, Nizhny Novgorod, Minsk) with salary 150,000 RUB. Involves developing complex ASIC functional modules using Verilog/SystemVerilog. Requires 3+ years of RTL development and simulator experience.

Develop complex functional modules for ASIC on Verilog/SystemVerilog.

Must have: - 3+ years of RTL development experience. - Knowledge of Verilog/SystemVerilog. - 3+ years of experience with RTL simulators (any vendor). - Experience working in Linux. - English: reading technical documentation and correspondence on technical topics. - Experience with version control systems. Nice to have: - Familiarity with make and scripting languages (perl/python/tcl/shell). - Experience programming in C/asm. - Experience with Altera and/or Xilinx FPGAs and corresponding software. - Familiarity with formal verification methods, SVA.

Format: hybrid, office (Moscow, Saint Petersburg, Nizhny Novgorod, Minsk). Bonuses for patent registration and creation of intellectual property results. Training portal with courses and lectures from external and internal experts, additional professional education, English learning, participation in conferences. Lecture hall with outstanding experts: engineers, scientists, and researchers. VHI from the first days of work, preferential insurance conditions for relatives. Consultations with lawyers, psychologists, experts in healthy lifestyle and financial management. Regular online meetings of the whole team.