Verification Engineer (FPGA/RTL)

Verification engineer for FPGA/RTL at Kraftway (Rosatom), Moscow. Full-time/hybrid/remote, salary negotiable.

Functional verification of IP blocks using UVM methodology; tracking bugs and interacting with developers; supporting regression testing/CI; creating verification plans.

3+ years in verification or RTL development for ASIC/FPGA (Verilog/SystemVerilog); knowledge of UVM; familiarity with modern processor architecture and SoC interfaces (ACE, AXI, APB); SystemVerilog Assertions; Linux; Git/GitLab; experience with third-party VIP; English for technical documentation. Nice to have: scripting (C, Python, TCL, shell); CI systems (Jenkins/GitLab + Cadence Vmanager); high-speed interfaces (PCI-Express, DDR, ONFI/Toggle); PCI-Express and network interfaces (xxMII, SFI, SFP); Atlassian products (Jira, Confluence).

Own R&D IT laboratory; official employment under Russian Labor Code; full social package including medical insurance; hybrid schedule; salary negotiable; IT accreditation; deferment from military service.