UVM Verification Engineer

Verification Engineer to verify IP blocks and SoC for modern processors using UVM and SystemVerilog. Salary from 250,000 RUB. Hybrid/office/remote in Moscow, Saint Petersburg, Nizhny Novgorod, Minsk.

You will verify IP blocks and SoC for modern processors, working with UVM and SystemVerilog. We offer the opportunity to influence architecture, participate in patent activities, and grow with a team of experts. Tasks: - Planning functional verification of IP blocks and SoCs, developing test plans. - Developing verification environments on UVM. - Test automation (Python/Perl/Tcl). - Running regression testing in CI. - Configuring VIP for interfaces (AXI, AHB, OCP, CHI). - Coordinating test plans with architects and RTL developers.

Must have: - Experience in verification and/or RTL development for FPGA or ASIC from 3 years. - Knowledge of SystemVerilog and OOP. - Experience with RTL simulators (any vendor). - Proficiency in scripting languages (Python/Perl/Tcl/Shell). - Confident Linux skills. - English — reading technical documentation, correspondence. - Familiarity with modern processor architecture. Nice to have: - Experience with UVM. - Programming in ASM, C. - Experience with CI. - Knowledge of interfaces AXI, AHB, OCP, CHI.

- Format: hybrid/office/remote (Moscow, Saint Petersburg, Nizhny Novgorod, Minsk). - Salary: discussed individually, above market. - VHI from the first days, insurance for close ones. - Bonuses for patents and R&D. - Training portal, English courses, conferences. - Consultations of lawyers, psychologists, healthy lifestyle experts.