PCB Layout Engineer (PCB routing)

PCB Layout Engineer at Trinity, Moscow. Full-time, on-site/hybrid. Routing multilayer PCBs, high-speed interfaces, stackup, production files. Salary discussed individually.

Responsibilities: - Routing printed circuit boards according to schematics and technical specifications: microcontrollers, drive drivers, interface blocks, power boards, storage backplanes. - Topology of high-frequency paths: Ethernet (RMII/RGMII + PHY), USB 3.x, differential pairs RS-422, clocking — meeting impedance, length matching and crosstalk minimization requirements. - Routing of computing-level boards: PCIe (x4/x16, GPU, expansion cards), memory lines (including DDR5), M.2/NVMe backplanes — strictly according to reference layout and platform manufacturer guidelines. - Creating board stackup and impedance calculation (Si9000/Polar), coordinating parameters with the fabrication plant. - Preparing production files (Gerber X2, drill, assembly, ODB++), performing DRC/DFM checks, forming a complete set for production. - Iterative refinement of topology based on test results: EMC, signal integrity (SI), thermal conditions; adjustments based on lab and mechanical engineer feedback (clearances, fasteners, airflow zones). - Interaction with schematic engineer: raising questions on ambiguous points, agreeing changes, controlling compliance of topology with schematic and PI/SI requirements.

Knowledge/experience: - Experience routing multilayer boards (6–10+ layers) with dense placement, multiple power domains and high-speed interfaces on external connectors. - Practical experience tracing high-speed interfaces: PCIe Gen3/4/5, USB 3.x, Ethernet 100/1000BASE-T (RMII/RGMII), differential pairs RS-422/485 with impedance and trace length control. - Confident command of one EDA tool: Altium Designer / Cadence Allegro / KiCad (expert level: rules, libraries, routing options, version control). - Understanding of signal integrity (SI) and power integrity (PI) principles, ability to apply basic control methods (via stitching, reference planes, keep-out zones, via fence, AGND/PGND separation). - Skills in calculating and justifying stackup, working with impedance calculation tools (Si9000, Polar), understanding plant technological limitations and DFM requirements. - Experience preparing and checking production data (Gerber, drill, assembly), ability to read and apply fab requirements, conduct EQ (engineering queries) with production. - Ability to work with reference designs of chipsets and platforms (x86 and similar), not to change critical nodes without calculation and approval. Nice to have: - Experience with BGA packages and fine pitch, strict DFM requirements, experience delivering projects to mass production. - Practical iterations based on EMC lab feedback: ability to quickly and correctly make edits to topology according to standards. - Working with 3D models (STEP) to check compatibility with enclosure and mechanics, interaction with mechanical engineer on mechanical constraints. - Knowledge of IPC/ESKD standards for design documentation, experience with component libraries and data management (Altium Concord Pro and similar). - Experience with boards for extended temperature range components, designing for conformal coating and harsh operating conditions.

Employment under the Labor Code of the Russian Federation. Full-time, on-site/hybrid. Salary discussed individually.