FPGA Engineer

FPGA engineer at PRM Dev for developing RTL on Verilog, control software in C, P4 logic integration, IP cores configuration in Vivado, implementing 10G Ethernet, UDP, IPv4/IPv6, PTP, SyncE protocols. Location: Belarus, Russia. Full-time, remote/hybrid/office. Salary: individually discussed.

Responsibilities: • Development and debugging of RTL on Verilog • Development of control software in C (Microblaze, Vitis) • Integration of P4 logic • Integration and configuration of IP cores in Vivado • Implementation of protocols: 10G Ethernet, UDP, IPv4/IPv6, PTP (IEEE 1588), SyncE • Work with interfaces: AXI4-MM / Stream / Lite • Integration of 10G, DDR4, PCIe (XDMA), SPI, I2C • Optimization of high-speed paths

Requirements: • Confident Verilog • Experience in C development • Understanding of FPGA architecture (Xilinx) • Experience with Vivado / Vitis • Understanding of Ethernet and UDP/IP • Experience with AXI • Experience in integrating 10G and PCIe Nice to have: • Experience implementing PTP Transparent Clock (P2P / E2E) • Experience with SyncE • Implementation of WRED or other congestion control algorithms • Optimization of high-speed datapath • Hardware processing of network traffic

Official employment